This invention relates generally to Static Random Access Memory (SRAM) devices and, more particularly, to SRAM devices that utilize a loadless four transistor design.
Manufacturers are designing smaller and more power efficient integrated circuits by improving CMOS processes and reducing device dimensions. Scaling is the process of modeling the changes in electrical behavior that result from reducing the device dimensions. In constant field scaling, for example, the voltage is scaled down as the device dimensions are reduced. Maintaining proper circuit operation by maintaining the appropriate stability margin is a design concern as the voltage is decreased. Many of these integrated circuits include arrays of SRAM cells. Failure to maintain the appropriate stability margin in a SRAM cell may result in a failure to retain data in the cell, a change in the data state of the cell while reading, or in an accidental write to the cell.
SRAM cell designs have progressed from a four transistor SRAM cell illustrated in FIG. 1 and a six transistor SRAM cell illustrated in FIG. 2 to a loadless four transistor SRAM cell illustrated in FIG. 3. The four transistor SRAM cell or NMOS resistor load cell, hereinafter referred to as the 4-T SRAM cell, occupies a relatively small area, but the fabrication of the passive loads involves relatively complex steps. Additionally, the 4-T SRAM cell can inadvertently become monostable or read unstable rather than maintaining its bistable characteristics. This stability problem has caused the 4-T SRAM to lose favor in SRAM cell design during the past few years. The six transistor SRAM cell, hereinafter referred to as the 6-T SRAM cell, is relatively stable and is able to operate at lower supply voltages than the 4-T SRAM. However, the 6-T SRAM cell is approximately 30% to 40% larger than the 4-T SRAM cell, and thus more expensive.
The problems associated with the 4-T SRAM cell and the 6-T SRAM cell have led to the development of the loadless four transistor SRAM cell, hereinafter referred to as the LL4TCMOS SRAM cell. The LL4TCMOS SRAM cell comprises a pair of NMOS pull-down transistors and a pair of PMOS access transistors. The LL4TCMOS SRAM is relatively small, although it is not as small as the 4-T SRAM cell as it incorporates CMOS devices. However, the LL4TCMOS SRAM cell design suffers from data retention and unintentional write problems such as failures attributable to the effects of leakage current and to the effects of noise.
The fundamental lower limit for the voltage scaling of the LL4TCMOS SRAM is dependent on the inherent transistor threshold voltage VTN drop for the NMOS pull-down transistors in the design of the LL4TCMOS SRAM cell. The cell must have sufficient voltage to maintain the stability margin over the pull-down VTN. The pull-down VTN decreases with an increase in temperature at a rate of approximately xe2x88x924 mV per degree C. for high substrate doping levels and xe2x88x922 mV/degree C. for low doping levels. These temperature variations pose a stability problem for low-voltage LL4TCMOS SRAM arrays. A higher pull-down VTN at lower temperatures may provide a voltage drop that causes an unacceptably low stability margin for an LL4TCMOS SRAM cell that is operating at a low voltage; and a lower pull-down VTN at higher temperatures increases leakage currents in the cell that can lead to data retention problems and yield loss.
Therefore, there is a need in the art to provide a system and method that overcomes these problems.
The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. The present subject matter provides a circuit with a transistor having a temperature-compensated threshold voltage, i.e. VT, and particularly provides a low-voltage LL4TCMOS SRAM array of cells that include NMOS pull-down transistors with a temperature-compensated VTN.
An increase in temperature significantly increases the leakage current and decreases the VTN in a LL4TCMOS SRAM cell, which causes significant data retention problems for the cell. According to one embodiment of the present invention, each NMOS pull-down transistor comprises a triple-well transistor, and the threshold voltage VT thereof is adjusted to compensate for changes in temperature. A temperature-based modulation of the VBB potential back-biases the P-well of the triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. Thus, the LL4TCMOS SRAM cells that include a temperature-compensated VTN will maintain the appropriate margins of failure at low-voltage operation over a range of temperatures.
One aspect of the present invention is a transistor body bias generator. One embodiment of the generator comprises a charge pump and a comparator. According to this embodiment, the charge pump is coupled to a body terminal of at least one triple-well transistor, and the comparator is coupled to the charge pump. The comparator includes a first input, a second input, and an output. The first input receives a temperature-independent reference voltage. The second input receives a VT-dependent voltage from the transistor(s), and the output presents a control signal to the charge pump based on the comparison between the temperature-independent reference voltage and the VT-dependent voltage. The charge pump selectively charges the body terminal of the triple-well transistor(s) in response to the control signal.
These and other aspects, embodiments, advantages, and features will become apparent from the following description of the invention and the referenced drawings.